RT Dissertation/Thesis
T1 Contributions to the design of high-performance digital systems using Field Programmable System-on-Chip platforms
T2 Contribuciones al diseño de sistemas digitales de altas prestaciones utilizando plataformas Field Programmable System-on-Chip
A1 Fernandez Molanes, Roberto
K1 2203 Electrónica
K1 3307.90 Microelectrónica
AB Field-Programmable System-on-Chip (FPSoC) systems contain processors, memory, high-speed communications and reconfigurable logic (FPGA) in a single chip. Using only a FPSoC chip complex digital systems can be implemented almost completely, where the processor and FPGA work simultaneously (software/hardware co-processing) obtaining lower power consumption and better performance than traditional multi-chip solutions.In spite of the promising characteristics of these devices, its penetration into industrial applications is still small.  The main reason is a lack of knowledge about the processor-FPGA interconnect, which acts many times as the bottleneck of the application. For this reason, the first part of the thesis is dedicated to do a deep study on those interconnect mechanisms, making time measurements in function of different parameters that can affect the data transfer speed. From these numeric values a set of design guidelines that permit to extract the full potential of these devices are developed.Based on the proposed guidelines, in the second part of the thesis the implementation of two of the most common implementations for these devices are carried out. On the one hand a sensor, typically built using more than one chip, is implemented. The sensor is a high accuracy frequency measurement system to be part of a QCM (Quartz Chrystal Microbalance) mass sensor. The FPGA is used to perform high accuracy frequency measurements in hardware and the processor provides intelligence and flexibility. For the second application example a software acceleration is implemented. In this case Particle Swarm Optimization (PSO) is implemented where the processor is in charge of the most part of the algorithm while the FPGA executes the most time-consuming parts of the algorithm in parallel in hardware to speed it up.
YR 2019
FD 2019-01-09
LK http://hdl.handle.net/11093/1114
UL http://hdl.handle.net/11093/1114
LA eng
DS Investigo
RD 20-sep-2024